A SiC-JFET (junction type field effect transistor made of silicon carbide) is used more and more recently as a power device, which has a high withstand voltage and is suitable for use in power electronics devices such as inverters, DC-DC converters and switching power sources.
Since the SiC-JFET has no gate oxide film, it is manufactured more easily than a SiC-MOSFET. Since the SiC-JFET is generally normally-on type, however, the SiC-JFET is not suitable for use in power electronics devices or the like in a vehicle, which requires high reliability.
For this reason, it is proposed to connect a SiC-JFET in cascode with a normally-off type MOSFET, which is made of Si (silicon) and has a low withstand voltage, thereby to provide a hybrid power FET, which operates as a normally-off type switching element as a whole.
For example, as shown in FIG. 8, a hybrid power device is manufactured by cascode-connecting a normally-on type SiC-JFET and a normally-off type Si-MOSFET. The SiC-JFET and the Si-MOSFET are n-channel type. In this hybrid power device, a resistor 8 is connected to the gate of the Si-MOSFET 4 as an input resistor. A SE terminal is provided for sensing purpose at a junction (between the source of the SiC-JFET 2 and the drain of the Si-MOSFET 4), at which two FETs 2 and 4 are connected to form a hybrid power FET. The drain of the SiC-JFET 2, the source of the Si-MOSFET 4 and the gate of the Si-MOSFET 4 form a drain D, a source S and a gate G of the hybrid power FET, respectively. Parasitic components (capacitances C1 to C3, inductance L and the like shown in FIG. 8) are likely to be formed in manufacturing processes and cause resonance. A diode 6 connected between the drain and the source of the Si-MOSFET 4 is a parasitic diode formed in a Si-MOSFET structure. The Si-MOSFET 4 is subjected to high voltages transiently although its withstand voltage is low.
As a solution to this drawback, it is proposed by patent document 1, for example, to provide a resistor 10 between the gate of the SiC-JFET 2 and the source of the Si-MOSFET 4 for lowering switching operation speed of the hybrid power FET.    Patent document 1: US 2002/0153938A1
The resistor 10 thus provided between the gate of the SiC-JFET 2 and the source of the Si-MOSFET 4 is effective to lower the switching speed for preventing transient application of high voltage to the Si-MOSFET 4 and occurrence of resonance. However, the lowered switching speed will adversely increase switching loss, which is caused when the hybrid power FET turns on.
According to the hybrid power device shown in FIG. 8, discharge occurs in two stages as indicated by A and B in FIG. 9, when the hybrid power FET turns on. Specifically, in the first stage A, the Si-MOSFET 4 turns on when a gate voltage Vg2 is applied. Since a SE terminal voltage is lowered responsively, the gate-source capacitance C2 of the SiC-JFET 2 discharges as indicated by Q1. The gate-drain capacitance C1 of the SiC-JFET 2 discharges as indicated by Q2 in the second stage B.
The switching loss can be reduced in the first stage A by increasing the switching speed and shortening the period A between time t1 and time t2. The voltage developed by the resistor 10 (gate voltage Vg2 of the SIC-JFET 2) changes in the negative direction at this time. It is however preferable that the gate voltage Vg2 is as high as possible, that is, the change in the negative direction is as small as possible, to maintain high switching speed.
In the second stage B, it is preferred to lower the switching speed for stabilization of operation because resonance is likely to occur. Although the voltage of the resistor (gate voltage Vg2 of the SiC-JFET 2) changes in the negative direction at this time as well, it is preferable that the gate voltage Vg2 is as low as possible. This is because the switching speed is lowered and hence the resonance can be suppressed more.
The resistor 10 in the proposed technology, however, is only effective to lower the switching speed. That is, even if the resistor 10 suppresses resonance in the second stage B, it adversely increases the switching loss in the first stage A.